ECOOP 2025
Mon 30 June - Fri 4 July 2025 Bergen, Norway
Thu 3 Jul 2025 14:00 - 14:30 at M209 - Session 2 Chair(s): Giorgio Audrito

Development of safety-critical systems needs stringent requirements specification and verification to prevent catastrophic failure. This research accounts for syntac-tic and semantic differences between two formal verification tools: FRET, which generates Linear Temporal Logic (LTL) from natural language requirements; WEST, which works with Mission-time LTL (MLTL) formulas. This study cre-ates tool support for the automatic translation of the temporal logic generated by FRET to the temporal logic format expected by WEST. This translation is syntac-tically bridging and semantically preserving with bidirectional traceability to pri-mal requirements. Our solution utilizes regular expression-based mapping, varia-ble normalization, and mission-time interval translation to transform FRET’s LTL specifications to WEST’s MLTL syntax. A proof-of-concept JavaScript translator iteratively constructed through case studies, was incorporated as a feature within the FRET tool. Comparative validation in collaboration with the MU-FRET and WEST teams confirmed the efficacy of the framework. This research demon-strates enhanced reliability and efficiency in safety-critical requirements engineer-ing, with future research on semantic equivalence verification, cloud-native de-ployment, and human-centric interfaces.

Thu 3 Jul

Displayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change

14:00 - 15:45
Session 2FTfJP at M209
Chair(s): Giorgio Audrito Università di Torino
14:00
30m
Talk
From LTL to MLTL: Exploring translation between temporal logic representations using FRET and WEST
FTfJP
Songyan Lai Department of Computer Science, Maynooth University, Rosemary Monahan Department of Computer Science & Hamilton Institute, Maynooth University
14:30
30m
Talk
Towards a Unifying Semantics Playground
FTfJP
Andrew Butterfield Trinity College Dublin
15:00
30m
Talk
Towards an Axiomitisation of Solidity Memory and Storage
FTfJP
Guilherme Horta Alvares Da Silva Chalmers University of Technology and University of Gothenburg, Wolfgang Ahrendt Chalmers University of Technology, Richard Bubel Technische Universität Darmstadt
15:30
30m
Talk
VeriFast’s separation logic: a higher-order(ish) logic without laters for modular verification of fine-grained concurrent programs
FTfJP
Bart Jacobs DistriNet, Dept. CS, KU Leuven
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