Memory persistency models define how Non-Volatile Memory (NVM) writes are handled. Though well-defined for Intel-x86 and Arm architectures, they lack empirical validation on real hardware. Traditional methods fall short, as test programs cannot reliably distinguish between volatile cache reads and NVM reads. Physical bus probing also faces limitations due to the persistence domain extending into unmonitored buffers within the memory controller.

To address the challenge of navigating the memory hierarchy for insights into persistency behaviours, we propose a methodical \emph{memory hierarchy timing attack}. By time-stamping instructions, we capture subtle timing variations that provide clues about the access destination within the memory hierarchy. Interpreting these timing patterns, however, requires a comprehensive understanding of both the underlying architecture and the specific characteristics of the application in use.

To further automate the validation process, we advocate the use of \emph{model learning} techniques. These techniques allow for the iterative refinement of models through black-box observations, facilitating a more scalable and dynamic approach to persistency validation across diverse hardware platforms.